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Design techniques for high-speed, high-resolution comparators

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2 Author(s)
Razavi, B. ; Center for Integrated Syst., Stanford Univ., CA, USA ; Wooley, B.A.

Precision techniques for the design of comparators used in high-performance analog-to-digital converters employing parallel conversion stages are described. Following a review of conventional offset cancellation techniques, circuit designs achieving 12-b resolution in both BiCMOS and CMOS 5-V technologies are presented. The BiCMOS comparator consists of a preamplifier followed by two regenerative stages and achieves an offset of 200 μV at a 10-MHz clock rate while dissipating 1.7 mW. In the CMOS comparator offset cancellation is used in both a single-stage preamplifier and a subsequent latch to achieve an offset of less than 300 μV at comparison rates as high as 10 MHz, with a power dissipation of 1.8 mW

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:27 ,  Issue: 12 )