Referenced Items are not available for this document.
A 2-GOPS, 60-MIPS DSP with a new vector-pipeline architecture (VDSP: vector digital signal processor) has been developed for video CODEC systems, using 0.8-μm CMOS technology. The VDSP is programmable and can be adapted to handle various standards for video coding, such as those of CCITT H.261, MPEG (Moving Picture Experts Group), and JPEG (Joint Photographic Experts Group). It also contains a discrete cosine transform (DCT) core as one of the special processing units used to enhance performance. The 12.38-mm×12.90-mm VDSP, which consists of approximately 930 K transistors, operates at a maximum clock rate of 60 MHz. The encoder and the decoder specified in CCITT H.261 (full-CIF mode at 15 frames/s or more, 64 kb/s) can be realized with only two VDSP chips and only one VDSP chip, respectively
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:27
,
Issue:
12
)
Date of Publication: Dec 1992
- Page(s):
- 1886 - 1894
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 4338292
- Digital Object Identifier :
- 10.1109/4.173119
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Dec 1992
- Sponsored by :
- IEEE Solid-State Circuits Society
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