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A high-speed digital neural network chip with low-power chain-reaction architecture

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3 Author(s)
Uchimura, K. ; NTT LSI Lab., Kanagawa, Japan ; Saito, O. ; Amemiya, Y.

A high-speed digital neural network chip adopts a polyhedric discrimination neuron (PDN) model and low-power chain-reaction (LCR) architecture that can reduce the power dissipation to one-fiftieth or less. The chip contains 832 fully implemented digital synapse units that form 13 neurons on a 10.3-mm×14.1-mm die using 0.8-μm CMOS technology. The synapse weights are updated using an external computer. A computational speed of 8 billion connections per second (GCPS) is achieved with low 54-mW power dissipation. The forward propagation time is 104 ns. These features make it possible to implement large-scale neural network chips and systems

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:27 ,  Issue: 12 )