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A two-chip 1.5-GBd serial link interface

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7 Author(s)
Walker, Richard C. ; Hewlett Packard Co., Palo Alto, CA, USA ; Stout, C.L. ; Jieh-Tsorng Wu ; Lai, Benny
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A silicon bipolar transmitter and receiver chip pair transfers parallel data across a 1.5-GBd serial link. A new `conditional-invert master transition' code and phase-locked loop that provide adjustment-free clock recovery and frame synchronization are described and analyzed. The packaged parts require no external components and operate over a range of 700 to 1500 MHz using an on-chip VCO. The line code and handshake protocol have been accepted by the serial-HIPPI implementor's group for serially transmitting 800-Mb/s HIPPI data, an ANSI standard, and by SCI-FI, an IEEE standard for interconnecting cooperating computers

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:27 ,  Issue: 12 )

Date of Publication:

Dec 1992

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