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NMOS IC's for clock and data regeneration in gigabit-per-second optical-fiber receivers

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2 Author(s)
Enam, S.K. ; Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA ; Abidi, A.A.

The design and performance of two essential analog circuits in optical-fiber receivers is described. A time-interleaved decision circuit is capable of regenerating 35-mV nonreturn-to-zero (NRZ) data inputs to full logic levels at 1.1 Gb/s with 10-11 bit error rate (BER), and a phase-locked loop (PLL) extracts the clock from a 2 23 long pseudorandom sequence at 1.5 Gb/s with 13-ps r.m.s. jitter. The two circuits have been implemented as 1-μm NMOS ICs, and in their core area dissipate 200 and 350 mW, respectively

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:27 ,  Issue: 12 )