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A 155-MHz clock recovery delay- and phase-locked loop

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2 Author(s)
Lee, T.H. ; Analog Devices, Wilmington, MA, USA ; Bulzacchelli, J.F.

The authors describe a completely monolithic delay-locked loop (DLL) that may be used either by itself as a deskewing element, or in conjunction with an external voltage-controlled crystal oscillator (VCXO) to form a delay- and phase-locked loop (D/PLL). By phase shifting the input data rather than the clock, the DLL and D/PLL provide jitter-peaking-free clock recovery. Additionally, the jitter transfer function of the D/PLL has a low bandwidth for good jitter filtering without compromising acquisition speed. The D/PLL described here exhibits less than 1° r.m.s. jitter on the recovered clock, independent of the input data density. No jitter peaking is observed over the 40-kHz jitter bandwidth

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:27 ,  Issue: 12 )