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An 8-b 650-MHz folding ADC

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2 Author(s)
J. van Valburg ; Philips Res. Lab., Endhoven, Netherlands ; R. J. van de Plassche

An 8-b 650-MHz folding analog-to-digital converter (ADC) with analog error correction in the comparators is presented. With an input frequency of 150 MHz, 7.8 effective bits are obtained. The ADC is implemented in a 1-μm 13-GHz triple-level interconnect bipolar process, requiring 850 mW from a single -4.5 V supply. The die size is 4.2 mm2

Published in:

IEEE Journal of Solid-State Circuits  (Volume:27 ,  Issue: 12 )