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Critical area analysis

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1 Author(s)
Walker, D.M.H. ; Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA

The critical area is the region on an integrated circuit where the occurrence of a catastrophic spot defect will cause a functional circuit fault. The author describes how to efficiently compute detailed critical areas with the VLASIC Monte Carlo yield simulator. Methods for reducing the computational cost are described, along with some application examples. An SRAM cell failure caused by an extra second metal defect is analyzed as an example

Published in:

Wafer Scale Integration, 1992. Proceedings., [4th] International Conference on

Date of Conference:

22-24 Jan 1992