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Design and Optimization of the Extended True Single-Phase Clock-Based Prescaler

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5 Author(s)
X. P. Yu ; VLSI Design, Zhejiang Univ., Hangzhou ; M. A. Do ; W. M. Lim ; K. S. Yeo
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The power consumption and operating frequency of the extended true single-phase clock (E-TSPC)-based frequency divider is investigated. The short-circuit power and the switching power in the E-TSPC-based divider are calculated and simulated. A low-power divide-by-2/3 unit of a prescaler is proposed and implemented using a CMOS technology. Compared with the existing design, a 25% reduction of power consumption is achieved. A divide-by-8/9 dual-modulus prescaler implemented with this divide-by-2/3 unit using a 0.18-mum CMOS process is capable of operating up to 4 GHz with a low-power consumption. The prescaler is implemented in low-power high-resolution frequency dividers for wireless local area network applications

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IEEE Transactions on Microwave Theory and Techniques  (Volume:54 ,  Issue: 11 )