CMOS
Referenced Items are not available for this document.
5-GHz Oscillator Array With Reduced Flicker Up-Conversion in 0.13-
Voltage supply scaling in CMOS processes requires lower inductance and higher capacitance in conventional LC oscillators. Forcing several LC oscillators to run in phase is a valuable means of achieving the wanted phase noise with practical values of inductances and capacitances. However, in-phase oscillator arrays suffer from the up-conversion of transistors' flicker noise, in the presence of oscillator mismatches. A multitank oscillator topology is proposed, which has superior tolerance to mismatches and removes this mechanism of noise degradation. In order to assess such topology, an 802.11 a-compliant VCO with four coupled oscillators has been designed in a 0.13-mum CMOS technology. A phase noise better than -120 dBc/Hz at 1-MHz offset has been achieved along the 4.7-5.9-GHz tuning range
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:41
,
Issue:
11
)
Date of Publication: Nov. 2006
- Page(s):
- 2457 - 2467
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 9159465
- Digital Object Identifier :
- 10.1109/JSSC.2006.883315
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 30 October 2006
- Issue Date :
- Nov. 2006
- Sponsored by :
- IEEE Solid-State Circuits Society
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