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A 231-MHz, 2.18-mW 32-bit Logarithmic Arithmetic Unit for Fixed-Point 3-D Graphics System

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5 Author(s)
Hyejung Kim ; Korea Adv. Inst. of Sci. & Technol., Daejeon ; Byeong-Gyu Nam ; Ju-Ho Sohn ; Jeong-Ho Woo
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A 32-bit fixed-point logarithmic arithmetic unit is proposed for the possible application to mobile three-dimensional (3-D) graphics system. The proposed logarithmic arithmetic unit performs division, reciprocal, square-root, reciprocal-square-root and square operations in two clock cycles and powering operation in four clock cycles. It can program its number range for accurate computation flexibility of 3-D graphics pipeline and eight -region piecewise linear approximation model for logarithmic and antilogarithmic conversion to reduce the operation error under 0.2%. Its test chip is implemented by 1-poly 6-metal 0.18-mum CMOS technology with 9-k gates. It operates at the maximum frequency of 231 MHz and consumes 2.18 mW at 1.8-V supply

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:41 ,  Issue: 11 )

Date of Publication:

Nov. 2006

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