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Modelling of multilayer on-chip transformers

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2 Author(s)
Tsui, C. ; Dept. of Electron. & Inf. Eng., Hong Kong Polytech. Univ. ; Tong, K.Y.

An analytical model has been proposed for multilayer stacked on-chip transformers, including the effects of the eddy current losses in the metal layers and Si substrate. The model gives good agreement with S-parameter measurements on structures fabricated using a four-metal-layer 0.35 mum CMOS process. It is shown that proper account of the eddy current losses is necessary to predict accurately the S-parameter characteristics of on-chip transformers at higher frequencies

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Microwaves, Antennas and Propagation, IEE Proceedings  (Volume:153 ,  Issue: 5 )