Cart (Loading....) | Create Account
Close category search window
 

An FPGA Implementation of a Competitive Hopfield Neural Network for Use in Histogram Equalization

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
3 Author(s)
Saif, S.M. ; Mentor Graphics Corp., Cairo ; Abbas, H.M. ; Nassar, S.M.

This paper presents a field programmable gate array (FPGA) implementation for a competitive Hopfield neural network (CHNN) to be used in image histogram equalization (HE). This algorithm is so computationally expensive that a viable hardware implementation is appealing provided that an efficient algorithm-to-architecture mapping can be achieved. The Xilinx Virtex-E was used for the hardware realization. An efficient use of the chip is outlined in the results.

Published in:

Neural Networks, 2006. IJCNN '06. International Joint Conference on

Date of Conference:

0-0 0

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.