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An FPGA Implementation of a Competitive Hopfield Neural Network for Use in Histogram Equalization

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3 Author(s)
Saif, S.M. ; Mentor Graphics Corp., Cairo ; Abbas, H.M. ; Nassar, S.M.

This paper presents a field programmable gate array (FPGA) implementation for a competitive Hopfield neural network (CHNN) to be used in image histogram equalization (HE). This algorithm is so computationally expensive that a viable hardware implementation is appealing provided that an efficient algorithm-to-architecture mapping can be achieved. The Xilinx Virtex-E was used for the hardware realization. An efficient use of the chip is outlined in the results.

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Neural Networks, 2006. IJCNN '06. International Joint Conference on

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