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The Geometry Effect of Contact Etch Stop Layer Impact on Device Performance and Reliability for 90-nm SOI nMOSFETs

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4 Author(s)
Chieh-Ming Lai ; Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan ; Yean-Kuen Fang ; Chien-Ting Lin ; Wen-Kuan Yeh

The thickness effects of a high-tensile-stress contact etch stop layer (HS CESL) and the impact of layout geometry (length of diffusion (LOD) and gate width) on the mobility enhancement of lang100rang/(100) 90-nm silicon-on-insulator (SOI) n-channel MOSFETs (nMOSFETs) were studied in detail. Additionally, the low-frequency characteristics were inspected using low-frequency noise investigation for floating body (FB)-SOI nMOSFETs. Experimental results show that a device with a 1100-Aring HS CESL has worse characteristics and hot-carrier-induced degradations than a device with a 700-Aring; HS CESL due to larger stress-induced defects. The lower plateau of the Lorentzian noise spectrum that was observed from the input-referred voltage noise Svg implies a higher leakage current for devices with a 1100-Aring HS CESL. On the other hand, it was found that devices with narrow gate widths have higher driving capacity for a larger fringing electric field and higher compressive stress in the direction perpendicular to the channel. Because of the more serious impact of compressive stress in a direction parallel to the channel, a device with shorter LOD experiences more serious performance degradation

Published in:

Electron Devices, IEEE Transactions on  (Volume:53 ,  Issue: 11 )