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Phase-Adjustable Pipelining ROM-Less Direct Digital Frequency Synthesizer With a 41.66-MHz Output Frequency

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5 Author(s)
Chua-Chin Wang ; Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung ; Jian-Ming Huang ; Yih-Long Tseng ; Wun-Ji Lin
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A high-speed phase-adjustable read-only-memory less direct digital frequency synthesizer employing trigonometric quadruple angle formula is presented. A ten-stage pipelining architecture is employed based upon decomposition of phase operands. Spectral purity is better than -130 dBc for the worst case spurious-free dynamic range. The resolution is up to 12 bits. Most importantly, the output sinusoidal frequency is higher than 40 MHz, which is far higher than the 32-MHz requirement of Korean personal communications system, global system for mobile communications, and Bluetooth. Neither any scaling table nor error correction tables are required. The maximum error is mathematically analyzed. The word length of each multiplier is carefully selected in the digital implementation such that the error range is limited and the resolution is preserved

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Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:53 ,  Issue: 10 )