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Leakage Biased pMOS Sleep Switch Dynamic Circuits

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2 Author(s)
Zhiyu Liu ; Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI ; Kursun, V.

In this brief, a low-overhead circuit technique is proposed to simultaneously reduce subthreshold and gate-oxide leakage currents in domino logic circuits. pMOS sleep transistors and a dual threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. A sleep transistor added to the dynamic node strongly turns off all of the high threshold voltage transistors. Similarly, a sleep switch added to the output inverter exploits the initially high subthreshold and gate-oxide leakage currents for placing a circuit into an ultimately low leakage state. The proposed circuit technique lowers the total leakage power by 56.1% to 97.6% as compared to standard dual threshold voltage domino logic circuits. Similarly, a 4.6% to 50.6% reduction in total leakage power is observed as compared to a previously published sleep switch scheme in a 45-nm CMOS technology

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Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:53 ,  Issue: 10 )