By Topic

A Short-Channel SOI RF Power LDMOS Technology With \hbox {TiSi}_{2} Salicide on Dual Sidewalls With Cutoff Frequency T \sim \hbox {19.3 }\hbox {GHz}

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Rong Yang ; Inst. of Microelectron., Singapore ; Li, J.F. ; Qian, H. ; Lo, G.Q.
more authors

In this letter, a CMOS-compatible silicon-on-insulator (SOI) RF laterally diffused MOS (LDMOS) technology is proposed based on TiSi2 salicide with SiO2/Si3N4 dual sidewalls. The use of dual sidewalls yields a large process margin for defining drift regions and preventing source-gate silicide bridging. This technology improves the cutoff frequencies and the maximum oscillation frequencies by 27%-42% and 14%-22%, respectively, for a gate length in the range of 0.5-0.25 mum. For the shortest 0.25-mum gate length, a record cutoff frequency of 19.3 GHz and a high breakdown voltage of 16.3 V are achieved simultaneously for SOI RF LDMOS. This LDMOS technology is suitable for 3.6-V-supply 0-3-GHz power RFIC applications

Published in:

Electron Device Letters, IEEE  (Volume:27 ,  Issue: 11 )