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Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation

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4 Author(s)
Datta, Animesh ; Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN ; Bhunia, S. ; Mukhopadhyay, S. ; Roy, K.

Under inter-die and intra-die parameter variations, the delay of a pipelined circuit follows a statistical distribution. This paper presents analytical models to estimate yield for a pipelined design based on delay distributions of individual pipe stages. Using the proposed models, it is shown that a change in logic depth and an imbalance between stage yields can improve the design yield and the area of a pipeline a circuit. A novel statistical methodology is developed to enhance yield of a pipelined circuit under an area constraint. Based on the concept of area borrowing, the results show that incorporating a proper imbalance among stage areas in a four-stage pipeline improves design yield up to 15.4% for the same area (and reduces area up to 8.4% under a yield constraint) compared with a balanced design

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:25 ,  Issue: 11 )