By Topic

On Constrained Pin-Mapping for FPGA–PCB Codesign

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Wai-Kei Mak ; Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu ; Lai, C.-L.

Field-programmable gate arrays (FPGAs) are commonly used in board designs. The authors consider the constrained FPGA pin-mapping problem in the FPGA-printed circuit board (PCB) codesign process. Unlike all previous works, which only saw constrained FPGA pin mapping as an independent chip-level problem, they take into account the connectivity of the FPGA with other components on the PCB to minimize the occurrence of net crossover and the PCB wirelength when computing a pin mapping. They propose an efficient tool, the versatile input/output (VIO) mapper, to automatically generate a proper pin-mapping upfront during the FPGA-PCB codesign process. Their input/output (I/O) mapper has a high level of flexibility. It can handle the different kinds of complex restrictions found in different FPGA devices. And it allows the PCB designers to lock down, say, the pin assignments for some critical signals before generating the assignments for the rest of the signals. Their mapper is based on an elegant 0-1 integer linear program (ILP) formulation. They show that due to the effective control of the number of integer variables and the use of a strong formulation (instead of an alternative weak formulation), their ILP-based approach is highly efficient in practice. It runs much faster than the mapping tool in Altera's Quartus II tool suite. In addition, they experimentally showed that the industrial tool's mapping algorithm is very far from optimal. For many instances on which Quartus II failed, feasible I/O mappings were found using the VIO mapper

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:25 ,  Issue: 11 )