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Highly-Parallel Decoding Architectures for Convolutional Turbo Codes

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3 Author(s)
Zhiyong He ; Dept. of Electr. & Comput. Eng., Laval Univ., Que. ; Fortier, P. ; Roy, S.

Highly parallel decoders for convolutional turbo codes have been studied by proposing two parallel decoding architectures and a design approach of parallel interleavers. To solve the memory conflict problem of extrinsic information in a parallel decoder, a block-like approach in which data is written row-by-row and read diagonal-wise is proposed for designing collision-free parallel interleavers. Furthermore, a warm-up-free parallel sliding window architecture is proposed for long turbo codes to maximize the decoding speeds of parallel decoders. The proposed architecture increases decoding speed by 6%-34% at a cost of a storage increase of 1% for an eight-parallel decoder. For short turbo codes (e.g., length of 512 bits), a warm-up-free parallel window architecture is proposed to double the speed at the cost of a hardware increase of 12%

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:14 ,  Issue: 10 )