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Wake-Up Logic Optimizations Through Selective Match and Wakeup Range Limitation

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2 Author(s)
Kuo-Su Hsiao ; Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan ; Chung-Ho Chen

This paper presents two effective wakeup designs that improve the speed, power, area, and scalability without instructions per cycle (IPC) loss for dynamic instruction schedulers. First, a wakeup design is proposed to aim at reducing the power consumption and wakeup latency. This design removes the read of the destination tags from the wakeup path by matching the source tags directly with the grant lines. Moreover, this design eliminates the redundant matches during the wakeup operations by matching the source tags with only the selected grant lines. Next, the second design explores a metric called wakeup locality to further reduce the area cost of the wakeup logic. By limiting the wakeup ranges for the instructions in the issue window, this design not only reduces the area requirement but also improves the scalability. The experimental results show that this range-limited-wakeup design saves 76%-94% of the power consumption and reduces 29%-77% in the wakeup latency compared to the conventional CAM-based scheme with only 5%-44% of the area cost in a traditional RAM-based scheme. The results also show that this design scales well with the increase of both the issue width and the window size

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:14 ,  Issue: 10 )

Date of Publication:

Oct. 2006

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