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Hybrid-Scheduling for Reduced Energy Consumption in High-Performance Processors

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3 Author(s)
Valluri, M. ; Syst. & Technol. Group, IBM Corp., Austin, TX ; John, L. ; Hanson, H.

This paper develops a technique that uniquely combines the advantages of compile-time static scheduling and hardware dynamic scheduling to reduce energy consumption in dynamically scheduled processors. In this hybrid-scheduling paradigm, regions of the application containing large amounts of parallelism visible at compile-time bypass the dynamic scheduling hardware and execute in a low-power static mode. Experiments on several media and scientific benchmarks demonstrate that the proposed scheme can provide significant reduction in energy consumption with negligible performance degradation

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:14 ,  Issue: 9 )

Date of Publication:

Sept. 2006

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