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Fast Decimal Floating-Point Division

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3 Author(s)
Hooman Nikmehr ; Dept. of Comput. Eng., Bu Ali Sina Univ., Hamedan ; Braden Phillips ; Cheng-Chew Lim

A new implementation for decimal floating-point (DFP) division is introduced. The algorithm is based on high-radix SRT division The SRT division algorithm is named after D. Sweeney, J. E. Robertson, and T. D. Tocher. with the recurrence in a new decimal signed-digit format. Quotient digits are selected using comparison multiples, where the magnitude of the quotient digit is calculated by comparing the truncated partial remainder with limited precision multiples of the divisor. The sign is determined concurrently by investigating the polarity of the truncated partial remainder. A timing evaluation using a logic synthesis shows a significant decrease in the division execution time in contrast with one of the fastest DFP dividers reported in the open literature

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:14 ,  Issue: 9 )