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11 GHz CMOS /spl Sigma//spl Delta/ frequency synthesiser

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2 Author(s)
Solomko, V.A. ; Chair of Circuit Design, Brandenburg Univ. of Technol., Cottbus ; Weger, P.

A fully integrated 11 GHz fractional-N PLL with a three-stage MASH SigmaDelta modulator with DC dither in all stages is implemented in a standard 0.13 mum CMOS technology. The synthesiser generates no fractional spurs at frequency offsets outside the loop bandwidth and a small number of fractional spurs with the power not exceeding -44 dBc within the loop bandwidth at the carrier frequency of 11 GHz

Published in:

Electronics Letters  (Volume:42 ,  Issue: 21 )