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A Reconfigurable Parallel Architecture for Image Computing

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4 Author(s)
Jian Li ; Autom. Inst., Nat. Univ. of Defense Technol., Changsha ; Xiangjing An ; Lei Ye ; Hangen He

Algorithms for image processing and computer vision are natural candidates for high performance computing systems. This paper presents a reconfigurable parallel architecture prototype for image processing base on large scale FPGA computing. The introduced architecture can cover a wide range of real-time computer vision applications from preprocessing operations to low-level interpretation. In order to reduce the memory accessing time and communication latency, prime memory system for neighborhood operations or other data structures and FPGA-based transfer interconnection networks were designed in the introduced prototype system. This proposed architecture allows the user to program the system in both high-level (soft-programming) and low-level (hard-programming)

Published in:

Intelligent Control and Automation, 2006. WCICA 2006. The Sixth World Congress on  (Volume:2 )

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