A Reconfigurable Parallel Architecture for Image Computing

Algorithms for Image processing and computer vision are natural candidates for high performance computing systems. This paper presents a reconfigurable parallel architecture prototype for image processing base on large scale FPGA computing. The introduced architecture can cover a wide range of real-time computer vision applications from pre-processing operations to low-level interpretation. In order to reduce the memory accessing time and communication latency, prime memory system for neighborhood operations or other data structures and FPGA-based transfer interconnection networks were designed in the introduced prototype system. This proposed architecture allows the user to program the system in both high-lever (soft-programming) and low-level (hard-programming).