Novel integration technique for flip-chip bonding circuit in wafer scale packaging

A novel integration technique for flip-chip bonding a circuit in wafer scale packaging is presented. The solder is a multilayered structure which consists of 95 at.% Sn and 5 at.% Au. The metal-to-metal bonding process was carried out around 230/spl deg/C in air. The solder bond pads have an area of 625/spl mu/m/sup 2/ with the height of 2.3/spl mu/m. To characterize the integration technique a variety of designs for a flip-chip interconnections are fabricated and measured for a flip-chip mounted coplanar waveguide (CPW). Modeled predictions of the design show significant performance improvement can be achieved by considering the impact of the substrate and associated parasitics on the mounted chip and transition region in the design. In this paper, we discuss design, modeling and measurement of wide band transition for flip chipped circuits in wafer scale packaging. A locally scaled flip-chip structure is proposed to compensate effective dielectric constant at the transition part of the interconnect.