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BIST of PCB interconnects using boundary-scan architecture

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4 Author(s)
A. S. M. Hassan ; Bell Northern Res., Ottawa, Ont., Canada ; V. K. Agarwal ; B. Nadeau-Dostie ; J. Rajski

The issues of printed circuit board (PCB) interconnect testing are addressed in the context of boundary-scan architecture. Boundary-scan architecture is treated here as the framework for a PCB level built-in self-test (BIST). A novel BIST method is developed which utilizes various features of the architecture. Boundary-scan architecture is shown to have the capability to generate time-efficient test vector sets. Response compaction within the boundary-scan chain is introduced to reduce shift out time as well as to simplify detection and diagnosis. However, the proposed BIST schemes require some extensions of the standard boundary-scan cells, and the schemes can work only if every boundary-scan cell of every IC on the PCB has the proposed extensions

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:11 ,  Issue: 10 )