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Silicon compilation of very high level language

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1 Author(s)
Kahrs, M. ; Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA

The design and implementation of a compiler for two very high level languages are addressed. The first language is a set language similar to VERS and SETL. The second language is a novel signal processing language. The compiler uses data flow and type information to constrain possible choices before choosing a possible implementation. Heuristic search is then used to choose from competing concrete implementations of abstract data types. Constraint propagation is used at every selection step to remove incompatible configurations from the search, thereby reducing the search space considerably. A microprogram control store is automatically generated. The output of the compiler is a parts list, a net list of module interconnections, and the fields of the control store

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:11 ,  Issue: 10 )