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Topological channel routing [VLSI]

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3 Author(s)
Haruyama, S. ; AT&T Bell Lab., Murray Hill, NJ, USA ; Wong, D.F. ; Fussell, D.S.

A VLSI two-layer channel router designed to find solutions which minimize both wiring area and number of vias simultaneously is presented. The method, called topological channel routing, analyzes the topological relationship of wires before the wires are mapped onto the channel. A unique layout design rule called an interleaving mesh is used. The interleaving mesh prohibits long wires on one layer from overlapping with wires on the other layer, and thus has smaller crosstalk of signals because of smaller capacitive couplings between those wires on different layers. Experimental results show that the algorithm generates very good solutions. For example, a height of 41 for Deutsch's Difficult Example without any parallel overlaps of wires has been obtained and simultaneously, with a via count of 186, which is one of the best results ever reported in the literature

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:11 ,  Issue: 10 )