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Evaluation of cache base network processor by using real backbone network trace

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3 Author(s)
Ishida, S. ; Sci. & Technol., Keio Univ. ; Okuno, M. ; Nishi, H.

In this paper a novel cache-based packet-processing-engine (PPE) architecture that achieves high packet-processing throughput with low-power consumption is proposed and evaluated. As network packets of the same header information appear repeatedly in a short time, a special cache, the so called header-learning cache (HLC), memorizes the packet-processing method and enables most packets to skip the execution at the processing units array. The implementation of the cache-based PPE architecture, P-Gear, was designed. Real backbone network trace was used to evaluate the performance of it. This P-Gear can achieve over 80 % cache hit rate using 4K/32K entry for access/core networks. Compared to conventional PPE, P-Gear can achieve 100-Gbps (gigabit per second) packet-processing throughput with only 36.5% of the die size and 32.6% of the power consumption required by the conventional PPE

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High Performance Switching and Routing, 2006 Workshop on

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