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Low complexity architecture for exponentiation in GF(2m)

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2 Author(s)
Hasan, M.A. ; Dept. of Electr. & Comput. Eng., Victoria Univ., BC, Canada ; Bhargava, V.K.

A pipeline bit-serial multiplier architecture for the Galois field GF(2m) is presented. A structure for finite field exponentiation is developed based on the multiplier. The structure is regular, area efficient and suitable for VLSI implementation for large fields.

Published in:

Electronics Letters  (Volume:28 ,  Issue: 21 )