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Architecture research and VLSI implementation for discrete wavelet packet transform

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4 Author(s)
Xu Mei-hua ; Sch. of Mech. Eng. & Autom., Shanghai Univ. ; Chen Zhang-jin ; Ran Feng ; Cheng Yu-lan

A discrete wavelet packet transform hardware design based on frame-partitioned architecture is presented in this paper. In the design of the processor, a kind of optimization technique of memory-the same address operation is proposed, which can decrease the size of the memory and raise the hardware utility efficiency. A two-buffer structure memory system is evolved to meet the real time request of the outside system, and the adoption of four-stage pipeline increases the real time data processing ability of the system. It is successfully synthesized and simulated with EDA tools and implemented in FPGA of Alter's EP20K200E. It is demonstrated that this kind of wavelet packet transform architecture can carry out the design objectives of real time, universal, parameterized and one-chip feasible

Published in:

High Density Microsystem Design and Packaging and Component Failure Analysis, 2006. HDP'06. Conference on

Date of Conference:

27-28 June 2006