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SDNN-3: A simple processor architecture for O(1) parallel processing in combinatorial optimization with strictly digital neural networks

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4 Author(s)
Nakagawa, T. ; Toyota Technol. Inst., Nagoya, Japan ; Kitagawa, H. ; Page, E.W. ; Tagliarini, G.A.

An architecture for high-speed and low-cost processors based upon SDNNs, (strictly digital neural networks) to solve combinatorial optimization problems within O(1) time is presented. Combinatorial optimization problems were programmed as a set selection problem with the k-out-of-n design rule, and solved by a cluster of SDN elementary processors in a discrete operation manner of TOH (traveling on hypercube), which is a rule for synchronized parallel execution. In all simulation cases, the latest SDNN-3 hardware achieved O(1) parallel processing in solving large-scale N-queen problems of up to 1200-queens. It was confirmed that all of the solutions are optimum, and that the SDNN processor always converges to global minima without any external one

Published in:

Neural Networks, 1991. 1991 IEEE International Joint Conference on

Date of Conference:

18-21 Nov 1991