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Ultra Low Power Current-mode Algorithmic Analog-to-digital Converter Implemented In 0.18 /spl mu/m CMOS Technology For Wireless Sensor Network

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2 Author(s)
Dlugosz, R. ; Poznan Univ. of Technol. ; Iniewski, K.

This paper reviews existing analog-to-digital converters (ADC) and compares them based on the power consumption metric. For applications where power consumption is of utmost importance, a novel 8-bit current mode Successive Approximation ADC (SAR) is proposed. Based on initial simulations made for CMOS 0.35 mum technology, it has been observed that the novel SAR architecture is very flexible i.e. it can be easily tuned to work with different frequencies and different power consumption values. In CMOS 0.35 mum technology the optimum frequency range is 25-350 kS/s, and power dissipation of the analog part of ADC ranges from 40 nW to 550 nW for 1 V power supply. The final post layout simulations of the chip designed in CMOS 0.18 mum technology were made for 0.55 V power supply. Entire (analog and digital circuits) SAR ADC working with the frequency of 250 kHz consumes only 580 nW

Published in:

Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Proceedings of the International Conference

Date of Conference:

22-24 June 2006

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