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Si Circuits Design Automation Using Ample Language

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2 Author(s)
Sniatala, P. ; Poznan Univ. of Technol. ; Rudnicki, R.

This paper presents AMPLE language utilization for a layout generation. A current mirror generator is described. Next, the proposed solution is presented as a part of a design flow for SI circuits. Another tool improving the design - Current Mirror Maker is also presented. This tool calculates transistors' sizes, which fulfil the given requirements of the circuit for the desired technology. The whole approach was practically verified during the design of fabricated testing chip

Published in:

Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Proceedings of the International Conference

Date of Conference:

22-24 June 2006

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