Referenced Items are not available for this document.
The design of a 625 MHz fully differential phase-locked loop (PLL) is described. The circuit incorporates a phase-frequency detector, a charge pump, a novel quadrature ring oscillator with a new active load and frequency dividers. This PLL CMOS circuit is used in the lock detector for aiding frequency acquisition for the clock and data recovery circuit. This circuit is supported by system and circuit (CMOS 0.35mum) level simulation by CPP simulator and HSPICE
Published in:
Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Proceedings of the International Conference
Date of Conference: 22-24 June 2006
- Page(s):
- 184 - 187
- Print ISBN:
- 83-922632-2-7
- INSPEC Accession Number:
- 9123634
- Conference Location :
- Gdynia
- Digital Object Identifier :
- 10.1109/MIXDES.2006.1706564
- Product Type:
- Conference Publications
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