A 625 MHz CMOS Phase-locked Loop Used In Lock Detector Application

The design of a 625 MHz fully differential phase-locked loop (PLL) is described. The circuit incorporates a phase-frequency detector, a charge pump, a novel quadrature ring oscillator with a new active load and frequency dividers. This PLL CMOS circuit is used in the lock detector for aiding frequency acquisition for the clock and data recovery circuit. This circuit is supported by system and circuit (CMOS 0.35mum) level simulation by CPP simulator and HSPICE