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A 2.5-Gb/s CMOS Clock And Data Recovery Circuit With A 1/4 Rate Linear Phase Detector And Lock Detector

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2 Author(s)
S. M. Alavi ; Tehran Univ. ; O. Shoaei

An OC-48 phase-lock clock and data recovery (CDR) circuit is proposed, supported by system and circuit (CMOS 0.35mum) level simulation for SONET (2.488/2.688-Gb/s) transceiver applications. The CDR circuit exploits quarter rate linear phase detector. A novel quadrature ring oscillator using new active inductor is also introduced that operates at quarter rate of the original clock. Also for frequency locking this paper uses a lock detector. Making use of the frac14 linear phase detector (PD) facilitates the design of voltage controlled oscillator (VCO) and eliminates 1:4 demultiplexer and frequency divider since this topology directly produces recovered data

Published in:

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.

Date of Conference:

22-24 June 2006