A merged equalizer/CDR circuit employs a parallel-path equalizer and triple-loop adaptation to achieve a binary data rate of 10 Gb/s. Realized in 0.13mum CMOS technology, the circuit adapts to FR4 trace lengths up to 24 inches with BER<10-13 while consuming 133 mW from a 1.6-V supply
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VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on
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