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A 70GOPS, 34mW Multi-Carrier MIMO Chip in 3.5mm/sup ~/

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3 Author(s)
Markovic, D. ; Berkeley Wireless Res. Center, California Univ., Berkeley, CA ; Brodersen, R.W. ; Nikolic, B.

An ASIC realization of the MIMO baseband processing for a multi-antenna WLAN is described. The chip implements a 4times4 adaptive singular value decomposition (SVD) algorithm with combined power and area minimization achieving a power efficiency of 2.1GOPS/mW in just 3.5mm2 in a 90nm CMOS. The computational throughput of 70GOPS is implemented with 0.5M gates at a 100MHz clock and 385mV supply, dissipating 34mW of power. With optimal channel conditions the algorithm implemented can deliver up to 250Mbps over 16MHz band

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VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on

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