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A 14-b 150 MS/s CMOS DAC with Digital Background Calibration

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5 Author(s)
H. -H. Chen ; Inst. of Commun. Eng., Nat. Tsing Hua Univ., Hsinchu ; J. Lee ; J. Weiner ; Y. -K. Chen
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A 14-b 150MS/s current-steering DAC with background calibration technique is demonstrated. Digital background calibration loop trims the static performance less than plusmn 0.55 LSB. The DAC achieves the spurious free dynamic range (SFDR) of 81dB at 1.6MHz and 67dB at 48.75MHz for sampling rate of 150MS/s. The DAC is implemented in a 0.35 mum CMOS process and active area is a 2.4times1.2 mm2

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2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.

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