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A 12-Bit 32 /spl mu/W Ratio-Independent Algorithmic ADC

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3 Author(s)
J. Jarvinen ; Electron. Circuit Design Lab., Helsinki Univ. of Technol., Espoo ; M. Saukoski ; K. Halonen

This paper describes a ratio-independent algorithmic ADC architecture that requires a single differential amplifier and a comparator. The prototype 12-bit, 41.67 kS/s ADC with an active die area of 0.055 mm2 is implemented in a 0.13mum CMOS. The power dissipation is minimized using a dynamically biased operational amplifier. With a 32 muW power dissipation, the ADC achieves 80 dB SFDR and 60 dB SNDR, resulting in a power FOM of 0.9 pJ/conversion

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2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.

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