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Notice of Violation of IEEE Publication Principles
"9.75/10.6GHz SiGe PLL for LNB Satellite Front-Ends Using Half-Rate Oscillators"
by Maxim, A.; Gheorghe, M.; Turinici, C.;
in the Digest of Technical Papers, IEEE Symposium on VLSI Circuits, 2006. Page(s):41 - 42
After careful and considered review, it has been determined that the above paper is in violation of IEEE's Publication Principles.
Specifically, Adrian Maxim admitted the information in the paper was falsified. In response to an inquiry on this misconduct, Mr. Maxim acknowledged that the following people who have been listed as co-authors on several of his papers are fabricated names and that he is the only author:
C. Turinici, D. Smith, S. Dupue, M. Gheorge, R. Johns, D. Antrik
Additionally, in papers by Mr. Maxim that have co-authors other than those listed above, it was discovered in some cases that he had not consulted with them while writing the papers, and submitted papers without their knowledge.
Although Mr. Maxim maintains that not all of the data is falsified, IEEE nevertheless cannot assure the integrity of papers posted by him because of his repeated false statements.
Due to the nature of this violation, reasonable effort should be made to remove all past references to the above paper, and to refrain from any future references.
A fully-integrated frequency synthesizer for DBS satellite front-ends was realized in a low cost 50GHz fT SiGe process. Two half-rate VCOs followed by Gilbert frequency doublers generate the 9.75/10.6 GHz LO signals with lower phase noise than a full-rate oscillator. The loop filter was integrated on-chip by using a passive feed-forward architecture, which provides a noiseless resistor multiplication