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A Multiphase Delay-Locked Loop for 0.125-2Gbps 0.18/spl mu/m CMOS Transmitter

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2 Author(s)
Y. Moon ; Silicon Image Inc., Sunnyvale, CA ; D. Shim

A 0.18-mum CMOS DLL generates equally-spaced multiphase clocks over 16times range from 31.25 to 500MHz using a duty-cycle corrector and a lock detector with 32times lock range, which is at least 3.5times wider comparing with conventional multiphase DLL's. Measured TX data eyes have <4% eye unevenness, which is equivalent to <1% clock unevenness, over the data rates of 0.125 to 2Gbps

Published in:

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers.

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