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An SRAM Design in 65nm and 45nm Technology Nodes Featuring Read and Write-Assist Circuits to Expand Operating Voltage

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10 Author(s)
Pilo, H. ; IBM Syst. & Technol. Group, Essex Junction, VT ; Barwin, J. ; Braceras, G. ; Browning, C.
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This paper describes a 32Mb SRAM that has been designed and fabricated in a 65nm low-power CMOS technology. The design has also been migrated to 45nm bulk and SOI technologies. The 68mm die features read and write-assist circuit techniques that expand the operating voltage range and improve manufacturability across technology platforms

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VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on

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