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A Vth-Variation-Tolerant SRAM with 0.3-V Minimum Operation Voltage for Memory-Rich SoC Under DVS Environment

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9 Author(s)
Morita, Y. ; Graduate Sch. of Natural Sci. & Technol., Kanazawa Univ. ; Fujiwara, H. ; Noguchi, H. ; Kawakami, K.
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This paper proposes a voltage-control scheme for an SRAM that makes a minimum operation voltage down to 0.3 V even on a future memory-rich SoC. A self-aligned timing control guarantees stable operation in a wide range of Vdd under DVS environment. A measurement result of a 64-kb SRAM in a 90-nm process technology shows that 30% power reduction is achieved at 100 MHz. The area overhead is only 5.6%

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VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on

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