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Advanced Junction Profile Engineering Featuring Laser Spike Annealing and Co-Implantation for Sub-30-nm Strained CMOS Devices

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5 Author(s)

We have developed a novel junction profile engineering using laser spike annealing (LSA) with co-implant and applied it to sub-30-nm strained CMOS devices. A 55% reduction in source-drain extension (SDE) resistance achieves a 15% improvement in the saturation on-current (I on) at a 28-nm gate length for PMOS. A reduction in the source-dram parasitic resistance enables an over 50% improvement in the linear on-current (Idlin) by capping layer stress on the 29-nm gate length, which is about a 10% increase in the Idlin improvement ratio compared to that of the control device, and a 28% of I on enhancement gave us Ion= 460 muA/mum for I off= 100 nA/mum at Vd= -1.0 V. For NMOS, low resistance SDE can be obtained without inducing the deterioration of the Vth-rolloff thanks to the halo profile modulation, and 6% of Ion enhancement was achieved at a 29-nm gate length, and I on= 925 muA/mum for Ioff= 100 nA/mum at V d= 1.0 V was obtained

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VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on

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