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Novel Approach to Reduce Source/Drain Series Resistance in High Performance CMOS Devices Using Self-Aligned CoWP Process for 45nm Node UTSOI Transistors with 20nm Gate Length

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10 Author(s)
Pan, J. ; AMD Corp., Hopewell Junction, NY ; Topol, A. ; Shao, I. ; Singh, D.
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This paper reports a novel, non-epitaxial raised source/drain approach to decrease the parasitic series resistance in nMOSFETs fabricated on UTSOI using a selective electroless metal deposition process. A metallic layer selectively deposited in the source/drain and gate nickel or cobalt silicide regions significantly reduces the parasitic external resistance in nMOSFETs with 10nm body thickness and gate lengths down to 20nm. This approach is fully compatible with a conventional CMOS process flow for both Co and Ni silicides and eliminates the added complexity of a conventional raised source/drain approach. The extremely high deposition selectivity of the process is confirmed through gate leakage measurements

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VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on

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