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High-Performance Cu-Interconnects with Novel Seamless Low-k SiOCH Stacks (SEALS) Featured by Compositional Modulation Process for 45nm-Node ULSI Devices

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23 Author(s)
Tagami, M. ; Syst. Devices Res. Labs., NEC Corp., Sagamihara ; Ohtake, H. ; Tada, M. ; Ueki, M.
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Damage-free, self-organized Cu dual-damascene (DD) interconnects have been developed for 45nm-node ULSIs with novel "seamless low-k SiOCH stacks" (SEALS) featured by compositional modulation in PECVD processes. In the SEALS (keff=2.9), a carbon-rich porous SiOCH (k=2.45) is stacked directly on an oxygen-rich porous-SiOCH (k=2.7) without etch-stop (ES) or buffer layer, while a non-porous, oxygen-rich SiOCH (k=3.1) is put on the top as the hard-mask (HM). Unique chemistry-controlled plasma-etching and CMP are essential to the damage-free, DD profile control without SiO2-HM and ES. The 140nm-pitched Cu line has only 85fF/mm (single-load) due to the low k eff, and the interconnect delay of 45nm-node CMOS ring oscillator is reduced by 10% referring to that of the 45nm-node DD interconnect with SiO2-HM and ES. The Cu DD interconnect with SEALS is a strong candidate for high-speed and low-power, 45nm-node ULSIs

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VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on

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