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Novel FUSI Strained Engineering for 45-nm Node CMOS Performance Enhancement

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10 Author(s)
Lin, C.T. ; Central R&D Div., United Microelectron. Corp., Hsin-Chu ; Hsu, C.H. ; Chen, L.W. ; Chen, T.F.
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FUSI metal gate with strained engineering is extensively investigated and reported for the first time. Enveloped FUSI (fully silicided) phase transfer and volume change induced stress exhibits 10% NMOS ION enhancement. Further, the second CESL (contact etch stop layer) induced stress raised another 8% NMOS ION gain. Although the first CESL on poly-gate top removed by FUSI CMP leads to 10% PMOS ION degradation, it can be recovered or further improved by a dual CESL process

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VLSI Technology, 2006. Digest of Technical Papers. 2006 Symposium on

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